The semiconductor industry currently uses different types of semiconductor-based imagers including charge coupled devices (CCD) and CMOS imager devices. Because of the inherent limitations in CCD technology, CMOS imagers have been increasingly used as low-cost imaging devices. A fully compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits is beneficial for many digital applications.
A CMOS image sensor circuit includes a focal plane array of pixel cells, each one of the cells including a photoconversion device, for example, a photogate, photoconductor, or a photodiode for accumulating photogenerated charge in a doped portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output transistor, which receives photogenerated charges, typically from a doped floating diffusion region, and produces an output signal which is periodically read-out through a row select access transistor. The imager may optionally include a transistor for transferring charge from the photoconversion device to the floating diffusion region or the floating diffusion region may be directly connected to or part of the photoconversion device. A transistor is also typically provided for resetting the diffusion region to a predetermined charge level before it receives the photoconverted charges.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the foregoing patents are hereby incorporated by reference herein in their entirety.
In a conventional CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of signals representing the reset state and a pixel charge signal. Photo-charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node through a transfer transistor. The charge at the floating diffusion node is converted to a pixel output voltage by the source follower output transistor.
A known three-transistor (3T) CMOS active pixel sensor (APS) design used in many applications contains a photodiode for producing charges which are stored at a diffusion region, a reset transistor for resetting the diffusion region charge, a source follower transistor having a gate connected to the diffusion region for producing an output signal, and a row select transistor for selectively connecting the source follower transistor to a column line of a pixel array. In a four-transistor (4T) CMOS configuration, a transfer transistor is employed to gate charges from the photodiode to the diffusion region.
FIG. 1 illustrates a diagrammatic side sectional view of a portion of a CMOS image sensor four-transistor (4T) pixel employing a n+ highly-doped floating diffusion region 10.
The CMOS image sensor pixel 100 generally comprises a charge collection region 35 of a photodiode 11 for collecting charges generated by light incident on the pixel, and a transfer transistor having a gate 60 for transferring photoelectric charges from the collection region 35 to the floating diffusion region 10. The floating diffusion region 10 is electrically connected to the gate of an output source follower transistor 40. The pixel 100 also includes a reset transistor having a gate 50 for resetting the floating diffusion region 10 to a predetermined voltage before charge is transferred thereto from the photodiode 11, the source follower transistor 40 which receives at its gate an electrical signal from the floating diffusion region 10, and a row select transistor 70 for selectively outputting a signal from the source follower transistor 40 to a column line 71 in response to a decoded row address driver signal applied to the gate of the transistor 70.
The exemplary pixel 100 of FIG. 1 employs pinned photodiode 11 having charge collection region 35 for converting photons to charge on a semiconductor substrate 2. The pinned photodiode 11 is termed such since the potential in the photodiode 11 is pinned to a constant value when the photodiode 11 is fully depleted. The pinned photodiode 11 has a photosensitive p-n junction region comprising a p− type surface layer 4 and a n− type photodiode region 35 e.g., a charge collection region, within a p− type type 6. The p− type region 6 is formed within semiconductor substrate 2. The two p− type regions 4, 6 cause the n− type photodiode region 35 to be fully depleted at a pinning voltage. Impurity doped source/drain regions having n− type conductivity are provided about the transistor gates 50 and 60. The floating diffusion region 10 adjacent to transfer gates 51, 61 is a common source/drain region for a transfer transistor having gate 60 and the reset transistor having gate 50.
In a typical CMOS image sensor, trench isolation regions 8 formed in a p-well active layer 6 and adjacent to the charge collection region 35 are used to isolate the pixels. The gate stacks for the pixel transistors are formed before or after the trench isolation regions are formed. The order of these preliminary process steps may be varied as is required or convenient for a particular process flow.
A transparent insulating layer 99 is typically formed over the pixel 100. Conventional processing methods are then carried out to form, for example, metal conductor 15 in the insulating layer to provide an electrical connection/contact to the floating diffusion region 10, and other wiring to connect gate lines and other connections in pixel 100. For example, the entire substrate surface may be covered with a passivation layer of e.g., silicon dioxide, BSG, PSG, or BPSG, as a transparent insulating layer 99, which is planarized and etched to provide contact holes, which are then metallized to provide contacts to diffusion node 10.
In conventional CMOS image sensors, electrons are generated from light incident externally and accumulate in the n− type photodiode region 35. These charges are transferred to the floating diffusion region 10 by the gate 60 of the transfer transistor. The source follower transistor 40 produces an output signal from the transferred charges.
A maximum output signal is proportional to the number of electrons extracted from the n− type photodiode region 35. The maximum output signal increases with increased electron capacitance or acceptability of the photodiode. The electron capacity of pinned photodiodes typically depends on doping levels and the dopants implanted to form regions 4, 6, and 35. In particular, regions 4 and 35 dominate the pinned photodiode's 11 capacitance. Accordingly, increasing the pinned photodiode's 11 capacitance is useful to allow capture of greater levels of photoconverted charges.
Reducing dark current of the photodiode 11 is also important in CMOS image sensor fabrication. Dark current is generally attributed to leakage in the charge collection region 35 of the pinned photodiode 11, which is strongly dependent on the doping implantation conditions of the photodiode. In particular, high dopant concentrations in p-type electrical connection region 23 typically increases dark current.
CMOS imagers further suffer from poor signal to noise ratios and poor dynamic range as a result of the inability to fully collect and store the electric charge collected in the region 35. Since the size of the pixel electrical signal is very small, the signal to noise ratio and dynamic range of the pixel should be as high as possible.
There is, therefore, a need for an active pixel photosensor for use in a CMOS imager which increases a pinned photodiode's capacitance and resistance to dark current. A method of fabricating such an active pixel photosensor is also desired.